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10 – System Drawings
DPN 402197 © TSS (International) Ltd Page 9 of 14
Figure 10–8: 401103-2 CPU Core
UCLK1
+5V GND
/STRB /STRB
RWL RWL
RAMCE RAMCE D0 TxD1
D0 A0 D1
D1 A1 D2
D2 A2 A0 D0 A0 D8 D3 RxD1
D3 A3 RWL /IOEN A1 D1 A1 D9 D4
D4 A4 /STRB RAMCE A2 D2 A2 D10 D5
D5 A5 A16 /E2CE A3 D3 A3 D11 D6
D6 A6 A17 /BOOTCE A4 D4 A4 D12 D7
D7 A7 A18 A5 D5 A5 D13
D8 A8 A19 A6 D6 A6 D14 A0
D9 A9 A20 A7 D7 A7 D15 A1 PU212
D10 A10 A21 A8 A8
D11 A11 A22 A9 /STRB A9 /STRB /ZRD PU213
D12 A12 A23 /RDY A10 RAMCE A10 RAMCE /ZWR
D13 A13 /RDY1 A11 A11
D14 A14 /RDY2 A 12 GND A12 GND /CSSCC1
D15 A15 A13 A13
D16 A16 A14RWLA14RWL
D17 A17 /RDY A15 A15 PU211
D18 A18 A16 A16 RxD2
D19 A19 /INT2
D20 A20
D21 A21 RAMCERAMCE SCCCLK TxD2
D22 A22
D23 A23 /STRB /BOOTCE
D24 A0 D16 A0 D24
D25 /STRB /RDY /E2CE A1 D17 A1 D25 UCLK2
D26 /RDY A2 D18 A2 D26
D27 RWL RWL /IOEN A3 D19 A3 D27 UCLK3
D28 A4 D20 A4 D28
D29 PU21 A5 D21 A5 D29
D30 A6 D22 A6 D30 D0 TxD3
D31 A7 D23 A7 D31 D1
A8 A8 D2
DR0 DX0 A9 /STRB A9 /STRB D3 RxD3
CLKR0 CLKX0 A10 RAMCE A10 RAMCE D4
FSR0 FSX0 A11 A11 D5
A12 GND A12 GND D6
/INT0 PU23 GND A13 A13 D7
/INT1 PU24 A14RWLA14RWL
/INT2 TCLK0 A15 A15 A0
/INT3 TCLK0 A16 A16 A1 PU215
TCLK1TCLK1
/ZRD PU216
/RESET XF0 /ZWR
CLK1 XF0 /BOOTCE/BOOTCE
XF1XF1 /E2CE /CSSCC2
EM0 H1H1
EM1 H3 A0 D8 A0 D0 PU214
EM2 EM3 H3 A1 D9 A1 D1
A2 D10 A2 D2 /INT3
A3 D11 A3 D3
A4 D12 A4 D4 SCCCLK
A5 D13 A5 D5
A6 D14 A6 D6
A7 D15 A7 D7
A8 A8
GND EM1 A9 /E2CE A9 /BOOTCE
A10 A10 GND /GPOEN
EM0 A11 A11
A12 A12 GND
EM2 A13 RWL A13
/INT0 A14 A14 D0 G0
CLK1 A15 D1 G1
A16 D2 DPD
EM3 A17 D3 APD
A18 D4 CMODE
CLK1 H3 D5
D6
D7
/GPOEN
CLK2
/GPOEN
CLKX0 /ADCEN GND
/CSSCC1
FSX0 /IOEN RWL /CSSCC2
/RESET DX 0
/ADCEN
/RESET CLK2
RWL /CSSCC1
+5V +5V PU29
/CSSCC1 /CSSCC2
A0 /CSSCC2
A1 /ZRD
A2 /GPOEN /ZRD
ACLK DR0 A3 /ADCEN /ZWR /ZWR
A8 /RESET
FSR0 A9 GND
A10
CLKR0 A11
A12
A13 /RDY1A /RDY1B
A14
A15
GND
PU210
SCCCLK
/RDY1
ACLK PU211
PU212
PU26 PU213
PU25 /ZRDY PU214
CLK2 PU26 PU21 H1 PU215
PU27 H1 PU216
/RESET PU28 PU23 RDY2 /RESET
PU29 PU24 /RESET PU28
PU210 PU25 PU27
/RESET EM0
/RESET /INT2 EM1
/INT3 EM2
/ZRDY
+5V
GND
ZRDY
/E2OE
/RDY
A[0..23]
TCLK0
TxD1
RxD1
TxD3
RxD3
TxD2
RxD2
D[0..31]
/INT1
/ADCEN
G0
G1
DPD
APD
CMODE
DTR1
+5V+5V
+5V
+5V
GND
GND
GND
+5V
GND
+5V
Title
Size Document Number Rev
Date: Sheet of
401103G2 G
PROCESSOR BOARD - CPU CORE
(C) TSS (UK) Ltd. 2001
ALL RIGHTS RESERVED
TSS 350 CABLE S URVEY SYSTEM
A2
24Tuesday, August 14, 2001
MISC PULLUPS
U1
ON DATA BITS 8-15
NOTE: U11 ACCESSED
DELAYED RDY
FROM U5
REQUESTS
READY SIGNAL
FROM WAIT-STATE
SCC2 CH 2 NOT
USED - BROUGHT
TO TESTPOINT
ONLY.
ONLY FITTED
FOR DEVELOPMENT
APPLICATIONS.
PIN 8 OMITTED
EMULATOR PORT
SERIAL PORT
ADAPTOR
SYNCHRONOUS
ONLY FITTED
FOR DEVELOPMENT
APPLICATIONS.
TO SHT 4
U1 U1 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U55
WAIT STATE GENERATOR - EACH STAGE ADDS 60ns
LOGIC TO CPU
ALL UNSPECIFIED CAPACITORS ARE PHILIPS 1206 SIZE,
100nF 63V X7R; PART NUMBER 1206-2R-104-K9AB
7.864325MHz
1.96608MHz
WATCHDOG DISABLE
(DEVT. USE ONLY)
ARTWORKED 1-2.
MI
1423
EDCCT
* Note issue 3 not used due
to part number errors
4
16 OCT 00
TWT
5**
G
RPM
1566
----
20APR001240
14 AUG 01
A
4
2
3*
DB
BY
DATE
DB
B
SWE
C
CHK
614
BB
2
GB
REVISION HISTORY
D
24SEP99
6
1579
2
2
NOs
08SEP95
21FEB95
ECR
REV
17APR00
BY
1676
PCB
F
ISS
** Issue 5 Not Used (Addition of Assy
revision box & PLCC sockets removed).
DB
TP2G
7
U12
27C040-250DC
A0
12
A1
11
A2
10
A3
9
A4
8
A5
7
A6
6
A7
5
A8
27
A9
26
A10
23
A11
25
A12
4
A13
28
A14
29
A15
3
CE
22
OE
24
O0
13
O1
14
O2
15
O3
17
O4
18
O5
19
O6
20
O7
21
A16
2
VPP
1
A17
30
A18
31
TP3I9
U10
5C1008DJ25
A0
12
A1
11
A2
10
A3
9
A4
8
A5
7
A6
6
A7
5
A8
27
A9
26
A10
23
A11
25
A12
4
A13
28
A14
3
A15
31
CE1
22
OE
24
D0
13
D1
14
D2
15
D3
17
D4
18
D5
19
D6
20
D7
21
WE
29
A16
2
CE2
30
DC18DC7
TP3P16
TP3O
15
TP6G
7
U9
5C1008DJ25
A0
12
A1
11
A2
10
A3
9
A4
8
A5
7
A6
6
A7
5
A8
27
A9
26
A10
23
A11
25
A12
4
A13
28
A14
3
A15
31
CE1
22
OE
24
D0
13
D1
14
D2
15
D3
17
D4
18
D5
19
D6
20
D7
21
WE
29
A16
2
CE2
30
U11
28C256S
A0
11
A1
10
A2
9
A3
8
A4
7
A5
6
A6
5
A7
4
A8
29
A9
28
A10
24
A11
27
A12
3
A13
30
A14
2
CE
23
OE
25
O0
13
O1
14
O2
15
O3
18
O4
19
O5
20
O6
21
O7
22
WE
31
DC11
TP1B
2
DC21
U3C
74ALS04
65
DC3
TP2H
8
TP6D
4
TP6B2 TP6C
3
DC14
U7
5C1008DJ25
A0
12
A1
11
A2
10
A3
9
A4
8
A5
7
A6
6
A7
5
A8
27
A9
26
A10
23
A11
25
A12
4
A13
28
A14
3
A15
31
CE1
22
OE
24
D0
13
D1
14
D2
15
D3
17
D4
18
D5
19
D6
20
D7
21
WE
29
A16
2
CE2
30
U8
5C1008DJ25
A0
12
A1
11
A2
10
A3
9
A4
8
A5
7
A6
6
A7
5
A8
27
A9
26
A10
23
A11
25
A12
4
A13
28
A14
3
A15
31
CE1
22
OE
24
D0
13
D1
14
D2
15
D3
17
D4
18
D5
19
D6
20
D7
21
WE
29
A16
2
CE2
30
TP6F
6
DC1
10u
DC22DC15
U3A
74ALS04
21
TP3D4
DC4
U4
74HCT16 4
SOIC
A
1
B
2
CLK
8
CLR
9
QA
3
QB
4
QC
5
QD
6
QE
10
QF
11
QG
12
QH
13
U57
74ALS574
D1
2
D2
3
D3
4
D4
5
D5
6
D6
7
D7
8
D8
9
CLK
11
OC
1
Q1
19
Q2
18
Q3
17
Q4
16
Q5
15
Q6
14
Q7
13
Q8
12
U3B
74ALS04
43
TP2P
16
TP3L12
U6
DS1232
SOIC
VCC
15
PB
2
TD
4
TOL
6
ST
13
RST
11
RST
9
GND
8
TP3F6
TP2F
6
U14
460020
CLK
1
RESET
9
Q0
12
Q1
13
Q2
14
Q3
15
RWL
2
CSPIT
4
CSSCC
5
ZRD
17
ZWR
18
RDY
19
NC3
3
NC6
6
NC7
7
NC8
8
EN
11
NC16
16
U16A
74ALS20
SOIC
1
2
4
5
6
U16B
74ALS20
SOIC
9
10
12
13
8
TP1A
1
TP3B2
TP2B
2
U15A
74ALS112
SOIC
Q
5
R
15
CK
1
K
2
J
3
S
4
Q
6
U15B
74ALS112
SOIC
Q
9
R
14
CK
13
K
12
J
11
S
10
Q
7
U17
Z85C3010VSC
D0
1
D1
2
D2
44
D3
3
D4
43
D5
4
D6
42
D7
5
A/B
39
D/C
37
/RD
41
/WR
40
/CE
38
IEO
7
IEI
8
/IACK
9
/INT
6
PCLK
23
TXDA
16
/RTXCA
13
/TRXCA
15
RXDA
14
/SYNCA
12
/WREQA
11
/DTRA
19
/RTSA
20
/CTSA
21
/DCDA
22
/DCDB
24
/CTSB
25
/RTSB
26
/DTRB
27
/WREQB
34
/SYNCB
33
RXDB
31
/TRXCB
30
/RTXCB
32
TXDB
29
TP2I
9
TP6E
5
TP2N
14
DC19
TP3C3
DC12
TP2C
3
U13
460025
RWL
1
IOEN
2
A0
3
A1
4
A2
5
A3
6
A8
7
A9
8
A10
9
A11
10
A12
11
A13
13
A14
22
A15
23
CSSCC1
14
CSSCC2
15
NC16
16
CSGPO
17
NC18
18
RDY2
21
CSADC
19
NC20
20
PL7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
U2
31.4573MHz
Q
8
TP7C
3
PL6
1
2
3
4
5
6
7
8
9
10
11
12
RP2
10k
1
2
3
4
5
6
7
8
9
DC8
U5
460018
STRB
2
RWL
1
A16
3
A17
4
A18
5
A19
6
A20
7
A21
8
A22
9
A23
11
IOEN
12
RAMCE
13
E2CE
14
BOOTCE
15
RDYOUT
19
RDYIN
18
RDY1D
16
RDY2D
17
TP3H8
TP7A
1
R2
100R
TP3E5
TP3J10
U56
74HCT161
SOIC
A
3
B
4
C
5
D
6
ENP
7
ENT
10
CLK
2
LOAD
9
CLR
1
QA
14
QB
13
QC
12
QD
11
RCO
15
TP3G
7
DC23
TP3N
14
TP1C
3
DC16
TP3K
11
DC5
U18
Z85C3010VSC
D0
1
D1
2
D2
44
D3
3
D4
43
D5
4
D6
42
D7
5
A/B
39
D/C
37
/RD
41
/WR
40
/CE
38
IEO
7
IEI
8
/IACK
9
/INT
6
PCLK
23
TXDA
16
/RTXCA
13
/TRXCA
15
RXDA
14
/SYNCA
12
/WREQA
11
/DTRA
19
/RTSA
20
/CTSA
21
/DCDA
22
/DCDB
24
/CTSB
25
/RTSB
26
/DTRB
27
/WREQB
34
/SYNCB
33
RXDB
31
/TRXCB
30
/RTXCB
32
TXDB
29
DC9
TP2D
4
DC2
TP7B
2
DC10
TP2J
10
TP7D
4
TP6A1
TP3M13
R9
100R
TP3A1
TP2K
11
DC20
RP3
10k
1
2
3
4
5
6
7
8
9
TP2L
12
TP2A
1
U1
TMS320C31PQL
A0
29
A1
28
A2
27
A3
26
A4
25
A5
23
A6
22
A7
21
A8
20
A9
18
A10
16
A11
14
A12
13
A13
12
A14
11
A15
10
A16
9
A17
8
A18
7
A19
5
A20
2
A21
1
A22
130
A23
129
D0
80
D1
79
D2
78
D3
77
D4
76
D5
75
D6
73
D7
72
D8
68
D9
67
D10
64
D11
63
D12
62
D13
60
D14
58
D15
56
D16
55
D17
54
D18
53
D19
52
D20
50
D21
48
D22
47
D23
46
D24
45
D25
44
D26
43
D27
41
D28
39
D29
38
D30
34
D31
31
VDD
6
VDD
15
VDD
24
VDD
32
VDD
33
VDD
40
VDD
49
VDD
59
VDD
65
VDD
66
VDD
74
VDD
83
VDD
91
VDD
97
VDD
104
VDD
105
VDD
115
VDD
121
VDD
131
VDD
132
VSS
3
VSS
4
VSS
17
VSS
19
VSS
30
VSS
35
VSS
36
VSS
37
VSS
42
VSS
51
VSS
57
VSS
61
VSS
69
VSS
70
VSS
71
VSS
84
VSS
85
VSS
86
VSS
101
VSS
102
VSS
109
VSS
113
VSS
117
VSS
119
VSS
128
X2/CLKIN
87
X1
88
RESET
95
STRB
93
RDY
92
R/WL
94
MCB/MPL
127
INT0
100
INT1
103
INT2
106
INT3
107
EMU0
124
EMU1
125
EMU2
126
EMU3
123
TCLK0
120
TCLK1
122
SHZ
118
DX0
116
CLKX0
112
FSX0
114
DR0
108
CLKR0
111
FSR0
110
IACK
99
XF0
96
XF1
98
HOLD
90
HOLDA
89
H1
81
H3
82
DC13
TP2M
13
U3D
74ALS04
89
TP1D
4
DC17
LK8
1
3
2
DC6
TP2E
5
RP1
22k
1
2
3
4
5
6
7
8
9
TP2O
15
- Cable Survey System 1
- System Manual 1
- GLOSSARY 13
- AMENDMENTS 14
- 1 INTRODUCTION 16
- 1.1 SYSTEM DESCRIPTION 20
- 1.2 PRINCIPLE OF OPERATION 21
- 1.3 QUICK START FOR SDC USERS 22
- 1.4 WARRANTY 22
- 2 SYSTEM OVERVIEW 24
- 2.1 SCOPE OF DELIVERY 25
- 2.2 UNPACKING AND INSPECTION 27
- 2.3 SURFACE COMPONENTS 28
- Figure 2–3: SDC Display 29
- Figure 2–4: SDC PC Console 29
- 2.4 SUB-SEA COMPONENTS 32
- 2.4.1 Sub-sea Electronics Pod 32
- ❐ Power/comms 33
- ❐ Altimeter 33
- ❐ Aux Output 33
- ❐ Sensor 33
- 2.4.2 Sensing Coils 34
- 2.4.3 Altimeter 36
- ❐ Tracked ROVs or crawlers 37
- ❐ Trenching ploughs 37
- ❐ Towed sleds 37
- 3 PHYSICAL INSTALLATION 38
- 3.1 SDC INSTALLATION 39
- 3.2 SUB-SEA INSTALLATION 40
- 3.2.1 SEP 40
- 3.2.2 Sensing Coils 42
- 3.2.2.1 Assembling the Coils 43
- 3.2.2.2 Mounting the Coils 46
- 3.2.3 Altimeter Installation 48
- 3.3 INSTALLATION CHECK LIST 50
- 4 ELECTRICAL INSTALLATION 52
- 4.1 SUB-SEA COMPONENTS 53
- 4.1.1 Ground Connections 54
- 4.1.3 Sub-sea Electronics Pod 55
- 4.1.3.1 Power Requirement 56
- 4.1.4 Sensing Coils 58
- 4.1.5 Sub-sea Altimeter 59
- 4.1.5.2 Connection to the SDC 60
- 4.1.6 Roll/Pitch Sensor 61
- 4.2 SURFACE DISPLAY COMPUTER 62
- 4.2.1 Power Connection 62
- 4.2.4 Interface to Video 68
- 5 SYSTEM CONFIGURATION 70
- 5.1 SOFTWARE INSTALLATION 71
- 5.2 POWER-ON PROCEDURE 72
- 5.3.1 SEP type 74
- 5.3.2 Communication ports 75
- 5.4 PRINT CONFIGURATION 77
- 5 – System Configuration 78
- 6 OPERATION SOFTWARE 80
- ONFIGURATION 81
- 6 – Operation software 84
- 6.2.1.2 Run/ Display screen 87
- the centre line. Measure 89
- ❐ Communication status 90
- ❐ System time 90
- ❐ System errors 90
- 6.2.1.3 Forward Search Screen 91
- 6.2.1.4 Other Windows 93
- ❐Yellow indicates an event 95
- 6.2.1.5 Configuration Options 97
- 6.2.2 Survey Parameters 97
- 6.2.2.1 Altimeter 99
- 6.2.2.2 External Data Logging 101
- 6.2.2.3 Load Factory Defaults 102
- 6.2.2.4 Video Overlay Setup 102
- 350 Cable Survey System 105
- 6.3 AFTER THE DIVE 107
- 6.4 REPLAYING A LOG FILE 108
- 6.5 QUALITY CONTROL 110
- 7 OPERATING PROCEDURE 112
- 7.1 BEFORE THE SURVEY 113
- 7.1.2 Tone Frequency 114
- 7.1.3 Survey Requirements 114
- 7.2 DURING THE SURVEY 115
- 7.2.2 Data Logging 117
- 7.2.3 Replay Logged Data 118
- 7.3 DATA FORMATS 119
- 7.3.1 External Logging Format 119
- 7.3.1.2 Forward Search mode 121
- ❐The target is out of range 122
- 7.3.2 Internal Logging Format 123
- 7.3.3 Altimeter Data Format 125
- 7.3.3.3 Simrad UK90 127
- 7.4 AFTER THE SURVEY 130
- 7.5.1 Operating Performance 131
- 7.5.2 Sources of Error 132
- 7.5.2.1 ROV Handling 132
- Figure 7–3: ROV roll errors 134
- Figure 7–4: Sloping target 136
- ❐ Changes of ROV heading 137
- ❐ Acoustic noise 137
- Figure 7–5: Curved target 139
- 7.6 ROVS 140
- 7.6.1 Speed of Operation 140
- 7.6.3 Tracked ROV 140
- 8 SYSTEM SPECIFICATIONS 142
- 8.1 SPECIFICATIONS 143
- 8 – System Specifications 144
- 8.1.2 Sub-sea Electronics Pod 145
- 8.1.3 Search Coil Array 145
- 8.2 PERFORMANCE 146
- 8.3 SYSTEM TRIALS 147
- 8.3.2 Results 149
- 8.3.2.1 Accuracy 149
- 8.4 UPDATE RATE 150
- 9 MAINTENANCE 152
- 9.1 CIRCUIT DESCRIPTION 153
- 9.1.1 Sensing Coils 154
- 9.1.2 Sub-sea Electronics Pod 155
- 9.1.2.2 Processor Board 156
- 9.1.2.3 Power Supply 158
- 9.1.3 Current Loop 158
- Page 8 of 26 159
- 9.2.2 Sub-sea Electronics Pod 160
- ❐ A 2.5mm hexagonal key 161
- Processor Board 162
- ADC Board 163
- 9.2.3 Coil Cable Continuity 166
- 9.3 FAULT IDENTIFICATION 167
- 9 – Maintenance 168
- 9.3.2 Communications Failure 169
- Page 20 of 26 171
- 9.3.4 Altimeter Failure 173
- Page 24 of 26 175
- Page 26 of 26 177
- 10 SYSTEM DRAWINGS 178
- 10 – System Drawings 180
- A OPERATING THEORY 192
- A.1 ELECTROMAGNETIC FIELDS 193
- A.2 FIELD DETECTION 193
- A.3 SIGNAL ISOLATION 194
- A.4 CALCULATION 195
- A.4.1 Survey Mode 196
- A.4.2 Forward Search Mode 198
- A.4.3 Skew Measurement 199
- B OPTIONS 202
- B.1 DUALTRACK SYSTEM 203
- B.1.1 The Equipment 203
- B.1.2 The Differences 204
- B.1.3 Scope of Delivery 205
- B.1.4 Physical Installation 207
- B.1.4.1 Search-coils 207
- B.1.4.2 Sub-sea Pods 207
- B.1.5 Electrical Connection 208
- B.1.5.1 System Configuration 210
- B.1.5.2 System Operation 211
- B.2 TRAINING 212
- C CABLES AND TONES 214
- C.1 TONE INJECTION 215
- C.1.1 Frequency Selection 215
- C.1.2 Connection to the cable 215
- C.1.2.1 Short cables 215
- C.1.2.2 Long cables 216
- C.1.2.3 Fibre-optic Cables 216
- C.1.3 Seawater Return Path 217
- D ALTIMETER 218
- D.2 INSTALLATION 219
- D.2.1 Electrical Connection 219
- D.2.2 Serial Output 219
- D.2.3 Mounting 220
- D.2.4 Maintenance 221
- D.2.5 Test in Air 221
- D.2.6 Internal Settings 221
- D.3 THEORY OF OPERATION 222
- D.3.1 Operating Principles 222
- D.3.1.1 Speed of Sound 223
- D.3.1.2 Terminology 223
- D.3.1.3 Propagation Loss 224
- D.3.1.4 Limitations 224
- D.3.2 Technical Description 225
- D.3.2.1 Power Supply 225
- D.3.2.2 Transmitter 226
- D.3.2.3 Receiver 226
- D.3.2.4 Sensor Circuitry 227
- D.3.2.5 Digital Circuitry 227
- D.3.2.6 Averaging Algorithm 228
- D.3.2.7 Optional Modem 228
- D.4 PART NUMBERS 228
- D.5 DRAWINGS 229
- D – ALTIMETER 230
- E COIL TESTER 236
- E.1 PRE-OPERATION 238
- E.2 OPERATION 240
- E.2.1 Frequency Selection 242
- E.3 FAULT IDENTIFICATION 243
- E.4 BATTERY REPLACEMENT 243
- E.5 MAINTENANCE 244
- E.6 SPECIFICATION 244
- F REFERENCE 246
- F.1 SURVEY DETAILS 248
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